Testing for the programming circuit of LUT-based FPGAs
نویسندگان
چکیده
T h e programming circuit o f look-up table based FPGAS consists of two shift registers, a control circuit and a configuration m e m o r y ( S R A M ) cell array. B e cause the configuration m e m o r y cell array can be easily tested by conventional tes t methods f o r R A M S , we f o cus o n testing for the shift registers. W e show that the testing can be done by using only the faculties of the programming circuit, wi thout using additional hardware.
منابع مشابه
Testing for the Programming Circuit of SRAM-Based FPGAs
The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of t...
متن کاملLook up Table Based Low Power Analog Circuit Testing
In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the ana...
متن کاملModule-based Synthesis of Behavioral Verilog Descriptions to Asynchronous Circuits
In this paper we present a design tool for automatic synthesis of Verilog behavioral description of an asynchronous circuit into delay insensitive presynthesized library modules, using syntax directed techniques. Our design tool can also generate appropriate output to support implementing the circuit on ASICs and LUT-based FPGAs consequently rapid prototyping of the asynchronous circuit becomes...
متن کاملLogic Circuit Design Implementation on FPGA at Reduced Dynamic Power Consumption
This paper introduces a new technique for reducing glitches in logic circuits implemented on Field Programmable Gate Arrays (FPGAs). The technique is based on the principles of path balancing. The main objective was to achieve glitch minimization which, in turn would reduce dynamic power during routing on FPGAs. The glitch aware routing was adopted for simulations tests. The input paths to look...
متن کاملConsequences and Categories of SRAM FPGA Configuration SEUs
Understanding the SEU induced failure modes specific to the Virtex SRAM FPGA is needed to evaluate the applicability of various mitigation schemes since many mitigation approaches were originally intended for ASICs and may not be effective or efficient within FPGAs due to the unique failure modes and architectures found in SRAM-based FPGAs. Through this work, we have shown that SEUs in FPGAs’ p...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1997